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RM0008
Figure 211. I 2 S block diagram
Tx buffer
Serial peripheral interface (SPI)
Address and data bus
MOSI/ SD
16-bit
BSY OVR MODF CRC UDR CH
ERR SIDE
TxE RxNE
MISO
Shift register
NSS/WS
16-bit
Rx buffer
LSB first
Communication
control
I2SCFG
[1:0]
I2SSTD
[1:0]
CKPOL DATLEN
[1:0]
CH
LEN
I2S I2SE
MOD
Master control logic
Bidi Bidi CRC CRC Rx
mode OE EN Next DFF only SSM SSI
SPI
baud rate generator
LSB
First
SPE BR2 BR1 BR0 MSTR CPOL CPHA
CK
I 2 S clock generator
I2S_CK
I2SMOD
MCK
MCKOE ODD
I2SDIV[7:0]
I2SxCLK
ai14748
The SPI could function as an audio I 2 S interface when the I 2 S capability is enabled (by
setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same
pins, flags and interrupts as the SPI.
The I 2 S shares three common pins with the SPI:
●
●
●
SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in simplex mode only).
WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
Doc ID 13902 Rev 9
599/995
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